1. Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly, to semiconductor memories operable under operation modes designated by a combination of externally applied two control signals. The present invention has particular applicability to dynamic random access memories (DRAMs).
2. Description of the Background Art
In recent years, semiconductor memories are used in various electric apparatuses such as computers. In particular, the demand for dynamic random access memories (hereinafter referred to as "DRAM") and static random access memories (hereinafter referred to as "SRAM") is expected to increase further in the future. While the present invention is applicable to semiconductor memories (for example DRAMs and SRAMs) operating under operation modes designated by a combination of two externally applied control signals, a description will be made of a DRAM in the following for the purpose of simplicity.
FIG. 1 is a block diagram of a conventional DRAM. With reference to FIG. 1, the DRAM comprises a memory cell array 1 having a plurality of memory cells arranged in rows and columns, an address buffer 4 receiving externally applied external address signals A0 to A10, a row decoder 2 for decoding row address signals RA0 to RA9 output from address buffer 4, a column decoder 3 for decoding column address signals CA0 to CA9 output from address buffer 4 and a sense amplifier 15 for amplifying the signals read from memory cell alley 1. The DRAM further comprises a RAS input circuit 100b receiving an external row address strobe signal (referred to as "RAS signal" hereinafter), a CAS input circuit 200b receiving an external column address strobe signal (referred to as "CAS signal" hereinafter) and a WE input circuit 300b receiving an external write control signal (referred to as "WE signal" hereinafter). RAS input circuit 100b generates an intern signal. CAS input circuit 200b generates an internal CAS signal in response to the external CAS signal. WE input circuit 300b generates an internal WE signal in response to the external WE signal.
Row decoder 2 selects a row, that is, a word line designated by row address signals RA0 to RA9 in response to the internal RAS signal. Column decoder 3 selects a column designated by column address signals CA0 to CA9 in response to the internal CAS signal. In other words, column decoder 3 turns on the transistors connected to the column designated by column address signals CA0 to CA9 in an I/0 gate circuit 5 to connect the bit lines in the designated column with an input buffer 6 or an output buffer 7.
Address buffer 4 receives external address signals A0 to A10 to apply row address signals RA0 to RA9 and column address signals CA0 to CA9 to row decoder 2 and column decoder 3, respectively, in an ordinary writing and reading mode. Address buffer 4 receives internal address signals Q0 to Q9 generated from a refresh counter 8 to apply row address signals RA0 to RA9 for refreshing to row decoder 2 in a refreshing mode. A refresh controller 9 controls refresh counter 8 in response to the internal RAS signal. It is pointed out that the operation modes of the DRAM are determined or controlled by the combinations of the internal RAS signal, the internal CAS signal and the internal WE signal.
In the ordinary writing and reading mode, data is transferred between I/0 gate circuit 5 and input buffer 6 or between I/0 gate circuit 5 and output buffer 7 on a 4-bit basis. When the internal WE signal is at a H level (a logical high)(in a reading mode), an I/0 controller 11 outputs data Dout read from memory cell array 1 through output buffer 7 in response to a row address signal RA10 and a column address signal CA10. When the internal WE signal is at a L level (logical low) (in a writing mode), I/0 controller 11 applies input data Din externally applied through input buffer 6, to I/0 gate circuit 5 on a 4-bit basis.
A test mode controller 14 detects an external designation of a test mode in response to the internal RAS signal, the internal CAS signal and the internal WE signal. That is, test mode controller 14 generates a test signal TE of a L level when the test mode is externally designated. Column decoder 3 decodes column address signals CA1 to CA9 when the L level test signal TE is applied. That is, column address bit CA0 is disregarded. As a result, the data transfer between I/0 gate 5 and input buffer 6 or output buffer 7 is performed on a 8-bit basis. When the L level test signal TE is applied, input buffer 6 and output buffer 7 operate to carry out data reading and writing on a 8-bit basis. In other words, when the test mode is externally designated, the testing operation for a memory cell is automatically started.
A start and an end of the test mode are designated according to the timing charts shown in FIGS. 2 and 3. With reference to FIG. 2, upon the designation of the start of the test mode, internal CAS signal and internal WE signal are caused to fall. This is followed by a fall of internal RAS signal at the time t1. When internal CAS signal and internal WE signal are at the L level, test mode controller 14 detects the designation of the start of the test mode in response to the fall of internal RAS signal. Consequently, test mode controller 14 generates a test starting pulse TS and a low level test signal TE.
Conversely, upon the designation of the end of the test mode, internal CAS signal is first caused to fall as shown in FIG. 3. Internal WE signal is held at the H level. When internal RAS signal falls (at time t2), test mode controller 14 detects the external designation of the end of the test mode by detecting the L level internal CAS signal and the H level internal WE signal. Consequently, test mode controller 14 generates a test ending pulse TR to raise test signal TE. It is pointed out that the timings of the signal changes shown in FIG. 3 are the same as those in a CAS before RAS refresh cycle.
FIG. 4 is a circuit diagram showing RAS input circuit 100b, CAS input circuit 200b and WE input circuit 300b shown in FIG. 1. Each of the input circuits 100b, 200b and 300b shown in FIG. 4 has the same circuit arrangement. For example, RAS input circuit 100b includes cascaded-inverters 21b and 31. Inverter 21b comprises a PMOS transistors Q13, Q18 and a NMOS transistor Q19 connected in series between a power supply Vcc and ground. An NMOS transistor Q14 is connected in parallel to transistor Q19. Transistors Q18 and Q19 are connected to receive external RAS signal at their gates. Transistors Q13 and Q14 are connected to receive an activating signal .phi. at their gates. Inverter 31 includes a PMOS transistor Q15 and an NMOS transistor Q16 connected in series between power supply Vcc and ground. A PMOS transistor Q17 is connected between power supply Vcc and the input node of inverter 31 to accelerate the charging of the input node. Transistor Q17 has a gate connected to the output node of inverter 31.
Inverter 21b has a threshold voltage V.sub.TRAS '. The threshold voltage value is determined according to a ratio of transistor size such as a channel width ratio of transistor Q18 to transistor Q19. Similarly, an inverter 22b has a threshold voltage V.sub.TCAS ' and an inverter 23b has a threshold voltage V.sub.TWE '. It is pointed out that the threshold voltage values of inverters 21b, 22b an 23b are conventionally set to the same value. That is, a ratio of transistor size of the transistors constituting inverters 21b, 22b and 23b is fixed, so that the threshold voltage values are accordingly fixed.
Therefore, these inverters 21b, 22b and 23b are manufactured to have a fixed threshold voltage. The threshold voltage of the manufactured inverters 21b, 22b and 23b might however fluctuate because of some problem in a manufacturing process of the DRAM. In particular, the threshold voltage V.sub.TRAS ' of inverter 21b in RAS input circuit 100b set to be smaller than the other threshold voltages V.sub.TCAS ' and V.sub.TWE ' causes such problems as follows.
FIGS. 5A to 5D are timing charts explaining the problems caused in the conventional input circuits 100b, 200b and 300b. With reference to FIG. 5A, it is assumed that the external RAS signal, the external CAS signal and the external WE signal have a voltage V.sub.IH as a H level and a voltage V.sub.IL as a L level. It is additionally assumed that the threshold voltage V.sub.TRAS ' for the external RAS signal is lower than the threshold voltages V.sub.TCAS ' and V.sub.TWE ' for the external CAS signal and the external WE signal. It is further assumed that the voltage V.sub.IH is lower than the threshold voltages V.sub.TCAS ' and V.sub.TWE ' and higher than the threshold voltage V.sub.TRAS '.
The internal RAS signal generated in response to the external RAS signal is at a H level until the time t11 as shown in FIG. 5B. The external RAS signal falls at the time t11, whereby the internal RAS signal falls accordingly. On the other hand, the internal CAS signal and the internal WE signal are maintained at a L level as shown in FIG. 5C. As a result, the test signal TE falls at the time t11 as shown in FIG. 5D, to cause the same situation as shown in FIG. 2. In other words, the test mode is started even though the start of the test mode is not externally required. In other words, the operation in the test mode is started although the operation in an ordinary reading or writing mode is required. This causes inconvenience in a test (a test at a factory) before a shipment of DRAMs as will be described later.
FIG. 6 is a block diagram of test mode controller 14 shown in FIG. 1. With reference to FIG. 6, test mode controller 14 comprises a CAS before RAS enable detection circuit 61 for detecting a fall of the internal CAS signal before a fall of the internal RAS signal, a WE before RAS enable detection circuit 62 for detecting a fall of the internal WE signal before a fall of the internal RAS signal and an RAS before CAS enable detection circuit 63 for detecting a fall of the internal RAS signal before a fall of the internal CAS signal. Upon a detection of a predetermined condition, the detection circuits 61, 62 and 63 cause detection signals REFA, REFB and REFC to fall, respectively. That is, when the designation of the start of the test mode is detected, detection circuits 61 and 62 output L level signals REFA and REFB, respectively. A test mode control circuit 64 applies the test starting pulse TS to a latch circuit 65 in response to the signals REFA and REFB. Latch circuit 65 generates the L level test signal TE by holding the pulse TS.
Conversely, the detection of the designation of the end of the test mode causes only the output signal REFA of detection circuit 61 to fall. Test mode control circuit 64 applies the test ending pulse TR to latch circuit 65 in response to the signal REFA. Latch circuit 65 causes the test signal TE to rise in response to the pulse TR. In addition, the designation of the RAS only refresh mode causes only the output signal REFC of detection circuit 63 to fall. Test mode control circuit 64 outputs the test ending pulse TR in response to the signal REFC, thereby causing the test signal TE to rise. RAS before CAS enable detection circuit 63 and a part of test mode control circuit 64 constitute a test mode reset inhibiting circuit 70.
FIG. 7 is a flow chart showing the order of the tests of a DRAM before the shipment. With reference to FIG. 7, first, a DC test is executed in step 51, wherein the DRAMs operate in an ordinary operation mode and the consumed current is measured. Then in step 52, a function test is executed. In the function test, it is examined whether the DRAMs perform a desired operation or not in several ordinary operation modes. In step 53, an input level margin test is executed. In the input level margin test, a range of a voltage level allowing a normal operation is measured by varying H or L voltage levels of externally applied input signal and control signals. In step 54, a timing margin test is executed. In the timing margin test, the limit is measured to which the DRAMs are not able to perform a desired operation in response to an externally applied control signal by varying a change timing of the control signal.
In the test steps 51 to 54 shown in FIG. 7, the examination is made as to whether the DRAMs meet a required standard or use and DRAMs which do not meet these requirements are considered to be defective (fail). Conversely, only the DRAMs meeting all these requirements are considered non-detective and shipped accordingly (pass). It is to be noted that in all the tests 51 to 54 shown in FIG. 7, the DRAMs should be operated in an ordinary operation mode at any time.
As the foregoing, the tests before shipment should be carried out under an ordinary operation mode according to the test sequence shown in FIG. 7. Thus, the change of an operation mode of the DRAMs from an ordinary mode to a test mode without an external request should be avoided. If the DRAMs are brought into an undesired test mode during the test sequence shown in FIG. 7, the test result shows a fail even though none of the DRAMs is defective. This means that a normal testing is prevented. Therefore, it is necessary to prevent such situations shown in FIGS. 5A to 5D from occurring during the tests before the shipment.